32º SIMPÓSIO SUL DE MICROELETRÔNICA

SIM 2017, Rio Grande
2 a 5 de maio de 2017 - Rio grande/RS


Correalizado por:


Inscrições

Categoria Até 25/04 Após 25/04
Não-sócios Sócio
SBC/SBMICRO/IEEE
Não-sócios Sócio
SBC/SBMICRO/IEEE
Profissionais R$ 300,00 R$ 200,00 R$ 500,00 R$ 320,00
Professores/Pesquisadores R$ 180,00 R$ 120,00 R$ 300,00 R$ 200,00
Estudantes de Pós-graduação R$ 120,00 R$ 90,00 R$ 150,00 R$ 150,00
Estudantes de Graduação/Técnicos R$ 65,00 R$ 40,00 R$ 120,00 R$ 90,00

FORMAS DE PAGAMENTO

Só estão disponíveis as formas de pagamento por cartão de crédito, transferência bancária de conta do Banco do Brasil e nota de empenho.

Para transferências bancárias de conta do Banco do Brasil deve-se entrar em contato com a SBC através do e-mail "faturamento@sbc.org.br".

Clique aqui para fazer sua Inscrição


CANCELAMENTO

A solicitação de reembolso da inscrição deve ser feita até 25/04/2017 e o valor máximo a ser reembolsado será de 80%, sendo que os 20% restantes devem cobrir os custos administrativos da inscrição.

Chamada de trabalhos

O 32º Simpósio Sul de Microeletrônica será realizado em Rio Grande, nos dias 2 a 5 de maio de 2017 em conjunto com a Emicro2017. O programa do evento refletirá o amplo espectro de temas e interesses de pesquisa compartilhados entre os pesquisadores da área de circuitos e sistemas, além de fornecer um fórum único para a troca de ideias e resultados. A Emicro2017 juntamente com o SIM2017 ofertará uma ampla gama de sessões especiais e palestras ministradas por especialistas proeminentes, abrangendo áreas-chave de pesquisa em microeletrônica.

Tópicos de Interesse (não restritos)

Projeto digital e analógico;
Projeto de sistemas em único chip;
Sistemas Embarcados;
Teste e Verificação de sistemas e circuitos;
Microssistemas e microssensores integrados;
Processamento Digital de Sinais;
Modelagem e caracterização de dispositivos;
Ferramentas de EDA para microeletrônica;
Processo e tecnologias de fabricação de CIs.

Hospedagem

Hotel Atlântico - Cassino

Preços promocionais para participantes do evento
Apto Luxo Apto STD Apto Pleno
SGL DBL SGL DBL SGL DBL TPL
R$ 120,00 R$ 150,00 R$ 105,00 R$ 120,00 R$ 85,00 R$ 100,00 R$ 120,00

Para usufruir dos valores promocionais, deve-se mencionar o nome do evento EMICRO/SIM no momento da reserva.



Submissão de Trabalhos


Submissão dos artigos: 03/02/2017
SUBMISSÃO PRORROGADA ATÉ O DIA 10/03/2017

Notificação de aceitação: 29/03/2017
Envio das versões finais: 10/04/2017


Informações para os autores

Os artigos devem ser escritos em inglês com no máximo 4 páginas em formato IEEE.
Os melhores trabalhos de graduação e pós-graduação serão convidados a submeterem versões estendidas para a JICS (Journal of Integrated Circuits and System, ISSN 1807-1953) e para a ICCEEG (Revista Jr de Iniciação Científica em Ciências Exatas e Engenharia, ISSN 2236-0093).


Programação Preliminar

2 de Maio, terça-feira

  • Local: CIDEC - SUL, Universidade Federal do Rio Grande
  • Ministrante: Vinícius Valduga de Almeida Camargo

  • Instituição do Ministrante: Universidade Federal de Pelotas

  • Local: Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

  • Ministrante: Débora Matos

  • Instituição do Ministrante: UERGS

  • Local:Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

  • Ministrante: Gilson Wirth

  • Instituição do Ministrante: Universidade Federal do Rio Grande do Sul

  • Local: Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

  • Ministrante: Alessandro Girardi

  • Instituição do Ministrante: UNIPAMPA

  • Local: Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

3 de Maio, Quarta-feira

  • Ministrantes: Renato Perez Ribas

  • Instituição do Ministrante: UFRGS

  • Local: Auditório 3 - CIDEC-SUL, Universidade Federal do Rio Grande

  • Ministrantes: Adão Souza Junior

  • Instituição do Ministrante: IFSUL-Pel

  • Local: Auditório 3 - CIDEC-SUL, Universidade Federal do Rio Grande

  • Ministrante: Ricardo Reis

  • Instituição: Universidade Federal do Rio Grande

  • Local: Auditório 3 - CIDEC-SUL, Universidade Federal do Rio Grande

  • SIM 1 – Analog and Mixed-Signal I
    Chair: To be defined
    Local: Auditório 3
    14:30 – 14:45: Complex-valued Three layer Perceptron for the Behavioral Modeling of RF Power Amplifiers. Luiza Freire and Eduardo Lima
    14:45 – 15:00: Design and Simulation of Integrated Inductors in CMOS Technology for Radiofrequency Circuits. Rodrigo Godinho Silva, Bernardo Rego Barros de Almeida Leite, Andre Augusto Mariano and Oscar Da Costa Gouveia Filho
    15:00 – 15:15: CMOS Rectifier Design for RFID Tag Used in Biomedical Implants. Lucas Castelan Prado, Fernando Rangel de Sousa and Fabian L. Cabrera
    15:15 – 15:30: Direct and Indirect Learning for Predistorter Design Using Data with Reduced Sampling Frequency. Joel Chavez and Eduardo Lima

  • SIM 2 – Electronic Design Automation I
    Chair: To be defined
    Local: Sala Estuários
    14:30 – 14:45: Placement Cells in FPGA. The Chaotic Place. Elias de Almeida Ramos, Guilherme Bontorin and Ricardo Reis
    14:45 – 15:00: Survey on Discrete Gate Sizing for leakage power minimization. Henrique Plácido, Jucemar Monteiro, Mateus Fogaça, Marcelo Johann and Ricardo Reis
    15:00 – 15:15: Study and Implementation of Routing Prediction Algorithms for VLSI. Eder Matheus Monteiro, Mateus Fogaça, Marcelo Johann and Ricardo Reis
    15:15 – 15:30: Technology Mapping for Emerging Technologies Based on a Novel Cut Enumeration Strategy. Augusto Neutzling, Jody Maick Matos, Andre Reis and Renato Ribas

  • SIM 3 – System on Chip I
    Chair: To be defined
    Local: Sala Lagoas
    14:30 – 14:45: System Management Recovery Protocol for MPSoCs. Vinicius Fochi, Luciano Caimi, Eduardo Wachter and Fernando Moraes
    14:45 – 15:00: TVD-SoC Software Architecture. Pedro Portugal, Ana L. Brod, Paulo Kipper and Altamiro Susin
    15:00 – 15:15: Improving the Efficiency of AES Encryption Algorithm by Using the Co-Designed Strategy. Ricardo Robaina and Bruno Neves
    15:15 – 15:30: Applying hardware and software codesign strategies in the implementation of the AES algorithm. Maurício de Souza Realan Arrieira, Lucidia Assunção Silveira and Bruno Silveira Neves

  • SIM 4 – Modeling and Simulation
    Chair: To be defined
    Local: Sala Ilhas
    14:30 – 14:45: RC Transistor Model for MIGFET. Jeferson José Baqueta, Andre Reis and Renato Ribas
    14:45 – 15:00: Analysis of Voltage Scaling in XOR Logic Gates using FinFET Devices. Leonardo H. Brendler, Alexandra L. Zimpeck, Ygor Aguiar, Cristina Meinhardt and Ricardo Reis
    15:00 – 15:15: Analysis of the Impact of the use of Schmitt Trigger Inverter on Process Variability for 32nm Technology in Full Adders. Samuel Toledo, Cristina Meinhardt and Paulo F. Butzen
    15:15 – 15:30: Non-volatile Memristive Memory Cell Simulation in SPICE Enviroment. Cesar Dias and Paulo F. Butzen
  • SIM 5 – Analog and Mixed-Signal II
    Chair: To be defined
    Local: Auditório 3
    16:00 – 16:15: TID effects on ADCs in a Mixed-Signal Design Diversity System. Carlos Julio Aguilera, Cristiano Chenet, Matheus Budelon and Tiago Roberto Balen
    16:15 – 16:30: Design of a low area gain compensated CIC decimation filter for the SBCD in 180 nm CMOS. Roberto Silva, Guilherme Araújo, Helga Dornelas and Marcelo Negreiros
    16:30 – 16:45: A CMOS Multiplexer Array For Reconfigurable Systems. Roberto Silva, Ana Carolina Xavier Silva Fonseca, José Amaral and Wilhelmus Van Noije
    16:45 – 17:00: Programmable Charge Pump Phase Locked-Loop for Clock Generation and Digital Driving. Raphael Ronald Noal Souza and Agord de Matos Pinto Jr.

    SIM 6 – Electronic Design Automation II
    Chair: To be defined
    Local: Sala Estuários
    16:00 – 16:15: Analysis of the Impacts of Diffusion and Polysilicon Gaps in Non-Series-Parallel Supergates. Maicon S. Cardoso, Gustavo H. Smaniotto, João J. S. Machado, Matheus T. Moreira, Leomar S. Rosa Junior and Felipe S. Marques
    16:15 – 16:30: Kernel Finder Post-processing Aiming Cell Layout Optimization. Gustavo Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato de Souza, Matheus Moreira, Felipe S. Marques and Leomar Rosa Jr.
    16:30 – 16:45: A Pseudo-Boolean Formulation to Address Minimum Diffusion Area Violations. Mateus Fogaça, Guilherme Flach, Marcelo Johann and Ricardo Reis
    16:45 – 17:00: Analytical Delay Model Automation for CMOS Logic Gates in SwitchCraft Framework. Gabriel Ammes, Felipe Marranghello, Andre Reis and Renato Ribas

    SIM 7 – System on Chip II
    Chair: To be defined
    Local: Sala Lagoas
    16:00 – 16:15: MPSoC Glass - An MPSoC IDE. Bruna Ramos de Carvalho, Bruno Endres Forlin and Cezar Reinbrecht
    16:15 – 16:30: Runtime Energy Management in MPSoCs. Vinicius Fochi, Luciano Caimi, Eduardo Wachter and Fernando Moraes
    16:30 – 16:45: Task Migration in Distributed Memory Many-Core Systems. Marcelo Ruaro and Fernando Moraes
    16:45 – 17:00: Self-aware Circuit Switching for NoCs. Marcelo Ruaro, Henrique Medina and Fernando Moraes

    SIM 8 – Digital Signal and Image Processing I
    Chair: To be defined
    Local: Sala Ilhas
    16:00 – 16:15: High Speedup Tiling Algorithm for Parallel HEVC Encoding. Iago Storch, Daniel Palomino, Bruno Zatt and Luciano Agostini
    16:15 – 16:30: Pruning and Approximation of Coefficients for Power-Efficient 2D Discrete Tchebichef Transform. Guilherme Paim, Leonardo Soares, Eduardo Costa and Sergio Bampi
    16:30 – 16:45: Energy Impact Assessment of the of HEVC Encoding Tools on Decoding Process. Douglas Corrêa, Daniel Palomino, Luciano Agostini and Bruno Zatt
    16:45 – 17:00: EEC – Electronic Elderly Care system. Laura Ramos, Lucas Lanzarini, Thanise Alano, Andre Braga and Calebe Conceicao

  • SIM 9 – Analog and Mixed-Signal III
    Chair: To be defined
    Local: Auditório 3
    17:00 – 17:15: Novel Identification Strategy for Compensation of IQ Modulator Imbalances and PA Nonlinear Distortions. Bruna Marcondes and Eduardo Lima
    17:15 – 17:30: Online Remaining Lifetime Prediction for Integrated Systems. Pedro Fausto Rodrigues Leite Junior and Frank Sill Torres
    17:30 – 17:45: Analysis of Phase Noise in MOS Enhanced Swing Colpitts Oscillator Operating in Moderate Inversion. Polyana Lacerda and Oscar Gouveia Filho.
    17:45 – 18:00: Study of the Impact of Initial Values in the Automatic Optimization of Analog IC Using PSO. Anderson Fortes, Robson André Domanski, Luiz Antônio Da Silva Junior and Alessandro Girardi

    SIM 10 – Test, Verification and Reliability I
    Chair: To be defined
    Local: Sala Estuários
    17:00 – 17:15: Development of a SEU fault injector for GPUs. Mateus Tirone, Márcio Gonçalves and José Rodrigo Azambuja
    17:15 – 17:30: An Assembly Fault Tolerance Approach to Detect SEUs in GPUs’ Vector Register File. Marcio Goncalves, Mateus Tirone and Jose Rodrigo Azambuja
    17:30 – 17:45: Automatic evaluation of gate realibility under permanent faults. Rafael Schvittz, Denis Franco, Lirida Naviner, Cristina Meinhardt and Paulo F. Butzen
    17:45 – 18:00: Evaluating the Behavior of Successive Approximation Algorithms under Soft Errors. Gennaro Rodrigues and Fernanda Kastensmidt

    SIM 11 – Digital Design I
    Chair: To be defined
    Local: Sala Lagoas
    17:00 – 17:15: High-Throughput Hardware Design for the HEVC Motion Estimation. Murilo Perleberg, Vladimir Afonso, Altamiro Susin, Luciano Agostini, Marcelo Porto and Bruno Zatt
    17:15 – 17:30: A Power-Efficient Imprecise Radix-4 Multiplier applied to High Resolution Audio Processing. Guilherme Paim, Leonardo Bandeira Soares, Eduardo Da Costa and Sergio Bampi
    17:30 – 17:45: High-Throughput Hardware Solution for the 3D-HEVC Depth Intra Skip. Luan Audibert, Vladimir Afonso, Altamiro Susin, Luciano Agostini, Bruno Zatt and Marcelo Porto
    17:45 – 18:00: Low Power Hardware Design for the HEVC IDCT Targeting Real-Time Applications. Jones Goebel, Ruhan Conceição, Bruno Zatt, Luciano Agostini and Marcelo Porto

    SIM 12 – Digital Design II
    Chair: To be defined
    Local: Sala Ilhas
    17:00 – 17:15: Interconnect Electromigration: Digital Design Flow Approach. Rute D. F. Queiroz, Leandro T. Manera and Roberto L. Orio
    17:15 – 17:30: Physical Implementation of a 32-bits RISC microprocessor using XFAB 600nm technology. Bruno Canal and Alexsandro Bonatto
    17:30 – 17:45: Voltage scaling impact on noise margin of 1-bit SRAM. Roberto Almeida, Clayton Farias, Paulo F. Butzen and Cristina Meinhardt
    17:45 – 18:00: Combining Addition Tree Schemes and Adders Topologies for 32bit Parallel Array Multipliers. Leandro Rocha, Guilherme Paim, Eduardo Da Costa and Sergio Bampi

4 de Maio, quinta-feira

  • Ministrante: Nikil Dutt

  • Instituição do Ministrante: University of California - Irvine

  • Bio: Nikil Dutt is a Chancellor's Professor of CS, Cognitive Sciences, and EECS at the University of California, Irvine.  He received a PhD from the University of Illinois at Urbana-Champaign (1989).  His research interests are in embedded systems, EDA, computer architecture and compilers, distributed systems, and brain-inspired architectures and computing. He has received numerous best paper awards and is coauthor of 7 books. Professor Dutt has served as EiC of ACM TODAES and AE for ACM TECS and IEEE TVLSI.  He is on the steering, organizing, and program committees of several premier EDA and Embedded System Design conferences and workshops, and has also been on the advisory boards of ACM SIGBED, ACM SIGDA, ACM TECS and IEEE ESL. He is an ACM Fellow, IEEE Fellow, and recipient of the IFIP Silver Core Award.

  • Sobre: We are seeing the emerging need for smartness in embedded systems that must address the (often conflicting) challenges of resiliency, energy, heat, cost, performance, security, etc. in the face of highly dynamic and autonomous operational behaviors and environmental conditions. Since terms related to “smartness” and "self-x" (e.g., self-awareness, self-adaptivity, autonomy, etc.) have been used loosely in many software and hardware computing contexts, I first present a taxonomy of "self-x" terms, and use this taxonomy to illustrate different levels of smartness in computing systems. A major attribute for smart embedded systems is the notion of self-awareness, that enables an embedded system to monitor its own state and behavior, as well as the external environment, so as to adapt intelligently. Towards this end, I present a smart embedded System-on-Chip (SoC) perspective using the CyberPhysical System-on-Chip (CPSoC) platform as an exemplar to demonstrate how embedded systems can achieve self-awareness.  Unlike traditional MultiProcessor Systems-on-Chip (MPSoCs), CPSoC is distinguished by an intelligent co-design of the control, communication, and computing (C3) system that interacts with the physical environment in real-time in order to modify the system’s behavior so as to adaptively achieve desired objectives and Quality-of-Service (QoS). The CPSoC design paradigm enables self-awareness (i.e., the ability of the system to observe its own internal and external behaviors such that it is capable of making judicious decisions) and (opportunistic) adaptation using the concept of cross-layer physical and virtual sensing and actuations applied across different layers of the hardware/software system stack. The closed loop control used for adaptation to dynamic variation -- commonly known as the observe-decide-act (ODA) loop -- is implemented using an adaptive, reflective middleware layer. The learning abilities of CPSoC provide a unified interface API for sensor and actuator fusion along with the ability to improve autonomy in system management.  I conclude with some thoughts on open challenges and research directions for smart embedded computing.

  • Local: Auditório 1 - CIDEC - SUL, Universidade Federal do Rio Grande

  • Ministrante: Jerome Mitard

  • Instituição do Ministrante: IMEC Bélgica

  • Bio: Jerome Mitard received the Ph.D. degree in microelectronic engineering from the Polytechnic University School of Marseille, France, in 2003. For three years, he acted as an STMicroelectronics assignee with CEA-LETI, Grenoble, France, where he was deeply involved in the electrical characterization of hafnium-based dielectrics with metal gate for sub-70 nm complementary metal–oxide–semiconductor (CMOS) technologies. After his Ph.D. in microelectronics at Micro and Nanotechnologies Campus Center, Grenoble, France, he joined the IMEC R&D center in Belgium, as a device researcher working on high-mobility devices for sub-10nm FinFET technology. He is currently Team Leader in charge of the 300mm Platform Device Research at IMEC and Principal Research Staff Member.

  • Sobre: Dr. Jerome Mitard, from IMEC R&D center, will lecture on advanced technology options required to achieve high speed operation of circuits and put them into the perspective of the end of the scaling roadmap of state-of-the-art but conventional silicon process technology. The introduction of high-k gate dielectrics and metal gates into advanced CMOS technology has re-opened the door to germanium and III-V compounds as potential replacements for silicon channels, offering the possibility to further increase the performance of future CMOS generations. Direct growth of both Ge and III/V in Si STI trenches is a very attractive option for co-integration of these materials on bulk Si substrates. Electrical passivation of the interface between the high-k dielectric and these materials remains a major challenge. An ultrathin Si capping layer of only a few monolayers thick was used to demonstrate short channel Ge pMOS devices with high drive currents. One of the key problems in developing inversion-mode III/V devices is the near mi gap Fermi level pinning associated with the high density of defect states present at the high-k /III-V interface. Various sulfide and other treatments have been investigated in great detail to passivate the surface. In combination with the proper high-k materials and deposition techniques, very good performance was demonstrated for both Ge and III/V devices. The introduction of these advanced materials also allows the development of new device concepts, such as the Implant-Free Quantum Well device.

  • Local: Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

  • Ministrante: Victor Grimblatt, Chile

  • Bio: Victor Grimblatt was born in Viña del Mar, Chile. He has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is currently R&D Group Director and General Manager of Synopsys Chile, leader in Electronic Design Automation (EDA). He opened the Synopsys Chile R&D Center in 2006. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore he is often consulted for new technological business development. Before joining Synopsys he worked for different Chilean and multinational companies, such as Motorola Semiconductors, Honeywell Bull, VLSI technology Inc., and Compass Design Automation Inc. He started to work in EDA in 1988 in VLSI Technology Inc. where he developed synthesis tools being one of the pioneers of this new technology. He also worked in embedded systems development in Motorola semiconductors. In 1990 he was invited by professor McCluskey to present his work in Logic Synthesis at the CRC – Stanford University. He has published several papers in EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, and Embedded Systems. From 2006 to 2008 he was member of the “Chilean Offshoring Committee” organized by the Minister of Economy of Chile. In 2010 he was awarded as “Innovator of the Year in Services Export”. In 2012 he was nominated to best engineer of Chile. He is also member of several Technical Program Committees on Circuit Design and Embedded Systems. Since 2012 he is Speaker of the IEEE Chilean chapter of the CASS. Victor Grimblatt is from 2002 professor of Electronics and IC Design in Universidad de Chile and Universidad de los Andes.

  • Sobre: The concept of Artificial Intelligence is not new. The technology world has been talking about that since the 80s. Some AI languages were already know in the 80s such as PROLOG and LISP. However we have not seen too many results until the last few years where the topic has become a trend topic in almost all publications and forums. What has changed? Is now a reality? This talk will try to answer those questions through the presentation of AI trends and the latest hardware and software technologies that allow the development of AI applications. The talk will also present current and next challenges of this technology.

  • Local:Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

  • Ministrante: Renato Hentschke, Intel USA

  • Bio: Renato Fernandes Hentschke received his bachelor’s, master’s, and Ph.D. degrees in computer science from the Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil. Since 2007, he has been with Intel Corporation, Hillsboro, OR, USA, where he is engaged in router engines and standard-cell synthesis engines. Prior to Intel, he was a temporary professor with the State University of Rio Grande do Sul (Guaiba, RS, Brazil) and interned with IBM, Yorktown Heights, NY, USA, as student for nine months. He holds a U.S. patent and has co-authored over 20 papers in the field of computer aided design of ICs. He is a reviewer of prestigious conferences, such as DAC and ICCAD. His current research interests include algorithms for physical design of VLSI circuits, such as placement, routing, and design rule modeling.

  • Sobre: This talk presents the usage of SAT/SMT solvers in two distinct angles. First, it will cover basic concepts of these solvers, how they can be used to solve general np-complete/hard problems of computer science (decision and optimization), and how these solutions compare with manually crafted heuristics. Second, the talk will discuss the use of these solvers into CAD tools. Recent process technologies impose strong gridding and very complex design rules; those challenges align well with SAT/SMT solvers in contrast with the traditional net-by-net approaches in CAD. Finally, the talk will focus on the problem of standard-cell synthesis using SAT/SMT with more in depth analysis of the transistor placement problem..

  • Local:Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

  • Moderador:Sérgio Bampi

  • Painelistas: Victor Grimblatt, Renato Hentschke, Jerome Mitard, Representante da empresa Keysight.

  • Local:Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

5 de Maio, sexta-feira

  • Ministrante: Carlos Silva Cárdenas

  • Instituição do Ministrante: PUC-Peru

  • Bio: CARLOS SILVA-CARDENAS, electronic engineer and PhD Universidad Autonoma de Barcelona.Principal professor in Catholic University of Peru. Director of Microelectronics Research Group and Director of Telecommunications Master Program. He has been General Chair of LASCAS2013, IBERCHIP2013 and Programm Chair ANDESCON2016 and anothers 8 events.

  • Sobre: It is well known that the permanent progress of integrated circuits manufacturing processes has a negative impact on the reliability of systems built from advanced circuits. The phenomena so-called Single Event Effect (SEE) gathers the different types of consequences resulting from the impact of a single energetic particle with a sensitive zone of a circuit. Many works shown that SEEs, which in the past strictly concerned space and avionics applications, may occur in applications operating in the earth’s atmosphere, even at sea level, mainly due to the consequences of the impact of neutrons in sensitive IC’s areas. Among SEEs must be mentioned the so-called Single Event Upset (SEU) which is the change of the content of a memory cell. In complex circuits such as processors, FPGAs, etc, SEUs usually called Soft Errors (SE), may propagate and thus provoke erroneous circuit’s results. Since 1993 the results of many “real-life” experiments (in balloons, aircrafts and high mountains) were published in the scientific literature. These experiments provided an objective feedback about the faults occurring in circuits including large sensitive areas, such as memories and Field Programmable Gate Arrays (FPGA), operating at different altitudes and allow validating solutions to guarantee the required dependability of targeted applications. Such experiments required huge numbers of parts because of the relatively low neutron flux (even at avionic altitudes) and the low sensitivity to SEUs of the used process technologies. Presently available technologies would allow designing real-life experiments with significantly lower number of parts and power consumption.

  • Local: Auditório 1 - CIDEC - SUL, Universidade Federal do Rio Grande

  • Ministrante: Michel Renovell

  • Instituição do Ministrante: CNRS, França

  • Bio: Michel Renovell received his MS and Ph.D. in applied physics both from the University of Montpellier, France. In 1986, he joined the Laboratory of Computer Science, Automation and Microelectronics of Montpellier where he is a researcher funded by the French National Council for Scientific Research (CNRS). From 1995 to 2005, he served as head of the Microelectronics teams at LIRMM (80 staff members). He has also been Director of the ‘French National Network on SOC/SiP Design & Test’. He is now Deputy-Director of LIRMM (400 staff members). In addition, he is Assistant-Director of the National Institute for Information Sciences CNRS-INS2I managing 62 French labs. He is a member of the editorial board of JETTA (the Journal of Electronic Testing: Theory and Application) and the editorial board of the VLSI Design Journal. From 2003 to 2005, he served as Vice-Chair of the IEEE TTTC (Test Technology Technical Council). Michel was general chair and program chair of many conferences (DTIS, DCIS, FPL, DELTA, DDECS, ETS, VTS…). He has published over 200 international papers, he has received 3 Best paper awards from different conferences. His research interests include: Defect modeling, Analog testing and FPGA testing. He is IEEE Fellow for his contribution to Defect analysis and Modeling.

  • Sobre: With today manufacturing technology, it is not possible to eliminate all defects and ensure every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to a customer. Different Test Strategies are commonly used since none is considered as optimal in terms of low defect level. Most companies use some but not all of the following three Test Strategies: the Static Voltage strategy, the Dynamic Voltage or Delay strategy, the Static or Dynamic Current (IDDX) strategy. While using different approaches, these different test strategies have a common objective: reveal the presence in the chip of defects or deviations that may create a dysfunction. Knowing the complexity of today defects, it is admitted that the classical fault models used for test generation cannot guarantee a satisfactory detection of defects. This implies that new test generation technique specifically oriented to defects have to be defined. So, we must analyze and understand the electrical behavior of the defect and describe its behavior through an adequate ‘defect model’. Then, defect simulation techniques and defect-oriented ATPG techniques must be proposed to allow specific test generation for these defects. This presentation focuses firstly on spot defects that manifest themselves as shorts or opens in the interconnect or in the MOS transistors. Secondly, the presentation focuses on new kind of defects appearing with the nanoscale technologies namely ‘the Global Defect’ such that IR-Drop or Ground Bounce.

  • Local: Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

  • Ministrante: Mateus Fogaça
  • Sobre: Due to the advanced stage of development on EDA science, it has been increasingly difficult to implement realistic software infrastructures in academia so that new problems and solutions are tested in a meaningful and consistent way. In this talk, we present Rsyn, a free and open-source C++ framework for physical synthesis research and development comprising an elegant netlist data model, analysis tools (e.g. timing analysis, congestion), optimization methods (e.g. placement, sizing, buffering) and a graphical user interface. It is designed to be very modular and incrementally extensible. New components can be easily integrated making Rsyn increasingly valuable as a framework to leverage research in physical design. Standard and third party components can be mixed via code or script language to create a comprehensive design flow, which can be used to assess better the quality of results of the research being conducted. The netlist data model uses the new features of C++11 providing a simple but efficient way to traverse and modify the netlist. Attributes can be seamlessly added to objects and a notification system alerts components about changes in the netlist. The flexibility of the netlist inspired the name Rsyn, which comes from the word resynthesis. Rsyn is created to allow researchers to focus on what is really important to their research spending less time on the infrastructure development. Allowing the sharing and reusability of common components is also one of the main contributions of the Rsyn framework. The key concepts of Rsyn are presented. Examples of use are drawn, the important standard components (e.g. physical layer, timing) are detailed and some case studies based on recent EDA contests are analyzed.

  • Local: Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

  • Ministrante: Maciej Ogorzalek

  • Bio: MACIEJ J. OGORZALEK is Professor of Electrical Engineering and Computer Science and Head of the Department of Information Technologies, Jagiellonian University Krakow, Poland – the oldest (1364) higher education institution in the country.He held several visiting positions in Denmark, Switzerland, Germany, Spain, Japan, Hong Kong.He received a Research Award from the Ministry of Education of Spain in 2000 and worked for one year at the National Microelectronic Center, Sevilla, Spain. In 2001 he received a Senior Award from the Japan Society for Promotion of Science as visiting professor at Kyoto University and in 2005 Hertie Foundation Fellowship at The Goethe Universty Frankfurt-am-Main. 2006-2009 he held the Chair of Biosignals and Systems, Hong Kong Polytechnic University under the Distinguished Scholars Scheme. Author or co-author of over 350 technical papers published in journals and conference proceedings, author of the book Chaos and Complexity in Nonlinear Electronic Circuits (World Scientific, 1997). He gave over 40 plenary and keynote lectures at major conferences world-wide. He served as Editor-in-Chief of the Circuits and Systems Magazine 2004-2007, Associate Editor for the IEEE Transactions on Circuits and Systems Part I, 1993-1995 and 1999-2001, he was elected Member of the Editorial Board Proceedings of the IEEE 2004-2009. He serves also as an Associate Editor – Journal of the Franklin Institute (1997-), Member of the Editoorial Board of the International Journal of Bifurcation and Chaos, Secretary of the Editorial Board for the Quarterly of Electrical Engineering (1993-2000), Member of the Editorial Board of Automatics (both in Polish), and Member of the Editorial board of the International Journal of Circuit Theory and Applications (2000- ) and Associate Editr of the NOLTA Journal IEICE Japan. Dr. Ogorzalek is IEEE Fellow (1997). He served the IEEE Circuits and Systems Society in various capacities including VP fpr Region 8, Administrative Vice-president and finally 2008 Society President. He was CAS Society Distinguished Lecturer(2004-2005) and received the 2002 Guillemin-Cauer Award, IEEE-CAS Golden Jubilee Award and IEEE CAS Meritorious Service Award. Currently he serves as IEEE Division 1 Director (2016-2017, Member of the IEEE Board of Directors. Until 206 he was Executive Vice-President of the Sniadecki Science Foundation in Poland. He is Member of the Polish Academy of Sciences (PAN) and Member of the European Academy of Sciences (Academia Europaea).

  • Sobre: As the sizing of transistors comes to the atomic distance limitations further development becomes possible by either introduction of new technologies or changing in geormetric arrangements of the elements and building blocks. Limitations in microcircuit constructions can be avoided by putting whole building blocks and sub-circuits in stacks. Such an approach allows for efficient space usage at the same time allowing circuit footprint reduction. Also routing solutions offer very significant wire-length reductions thus reducing power dissipations and signal delays. 3D integration looks as a fantastic new area of development, however, there are many new challenges and problems to be solved. 3D integration offers also unprecedented opportunities by allowing blocks fabricated in heterogeneous technologies to be integrated in one chip. This allows for stacking and integration of microprocessors, memories, RF circuitry, sensors, batteries and hyper-capacitors, energy harvesting blocks, biological and chemical sensors and many new types of building blocks in one chip.

  • Local: Auditório 1 - CIDEC-SUL, Universidade Federal do Rio Grande

  • SIM 13 – Test, Verification and Reliability II
    Chair: To be defined
    Local: Auditório 3
    16:00 – 16:15: Fault Collapsing Analysis Using BDDs Extensions. Gabriel Porto, Paulo F. Butzen and Denis Franco
    16:15 – 16:30: USAG: A semi-automatic tool for generating verification environments using the UVM methodology. Vinícius Bittencourt Da Silva and Alessandro Gonçalves Girardi
    16:30 – 16:45: Applying Lockstep in Dual-Core ARM Cortex-A9 to Mitigate Radiation-induced Soft Errors. Ádria Oliveira, Lucas Antunes Tambara and Fernanda Kastensmidt
    16:45 – 17:00: Built-in Signal Pattern Generator for Digital Integrated Circuit Testing. Pablo Rafael Bodmann, André Inácio Reis and Renato Perez Ribas
    17:00 – 17:15: A Tool for Reliability Analysis of Logic Circuit. Rafaél Ígor Fritz, Denis Teixeira Franco and Paulo Francisco Butzen
    17:15 – 17:30: Analysing Permanent Fault Effects on Majority Voters. Ingrid Oliveira and Paulo Butzen

    SIM 14 – Digital Design III
    Chair: To be defined
    Local: Sala Estuários
    16:00 – 16:15: Register-Transfer Level Design and Appraisal of Float Point Multipliers for Robot Applications. Lucas Caetano Meireles Pereira, Valquiria Huttner, Cristiano Steffens, Vagner Rosa and Silvia Botelho
    16:15 – 16:30: Design and Implementation of a Floating Point Unit for Real-time Control Applications. Lucas Caetano Meireles Pereira, Valquiria Huttner, Cristiano Steffens, Vagner Rosa and Silvia Botelho
    16:30 – 16:45: Exploiting Adder Circuits in the Recombination Line of Adder Compressors for Low Power Applications. Morgana Macedo Azevedo Da Rosa, Bianca Silveira, Leonardo Soares, Cláudio Diniz and Eduardo Antônio César Da Costa
    16:45 – 17:00: Implications of Work-Function Fluctuation on Radiation Robustness of XOR Circuits at 7nm FinFET. Ygor Quadros De Aguiar, Cristina Meinhardt and Ricardo Reis
    17:00 – 17:15: An Hardware-Synthesizable IP-Core for Floating-Point Arithmetic Operations. Luciano Braatz, Luciano Agostini, Bruno Zatt and Marcelo Porto
    17:15 – 17:30: An FPGA-Based Sinusoidal Signal Generator Using Recurrence Equation and PWM Output. Mateus Leme, Luciano Braatz, Luciano Agostini, Bruno Zatt and Marcelo Porto

    SIM 15 – Digital Signal and Image Processing II
    Chair: To be defined
    Local: Sala Lagoas
    16:00 – 16:15: A Kernel-Based Algorithm for Edge Detection in Multispectral Images. Luana R. Schulz, Wemerson D. Parreira and Sérgio J.M. Almeida
    16:15 – 16:30: Automatic TV Advertisement Clustering Based on Audio Features from Broadcasted Signal. Arthur Sofiatti, Natália Rovaris, Igor Hoelscher, Joel Luft, Tiago Balen and Altamiro Susin
    16:30 – 16:45: 3D Residual Coding Analysis for Video Coding. Mateus Melo, Gustavo Smaniotto, Bruno Zatt and Marcelo Porto
    16:45 – 17:00: A Rendering Framework for Point Cloud Visualization. Arthur Sofiatti, Fábio Pereira, Gustavo Ilha, Tiago Balen and Altamiro Susin
    17:00 – 17:15: Proposal of a pre-processing flow for DEMA attacks in cryptosystems with temporal misalignment countermeasures. Rodrigo Lellis and Rafael Soares

    SIM 16 – Embedded Systems
    Chair: To be defined
    Local: Sala Ilhas
    16:00 – 16:15: Profiling Tool for Processors. Rafael Cristiano Schneider and Bruno Silveira Neves
    16:15 – 16:30: Applying the Differential Collision Cache Attack on MPSoCs. Bruno Forlin, Bruna Carvalho, Cezar Rodolfo Wedig Reinbrecht and Altamiro Susin
    16:30 – 16:45: Using gem5 and CACTI to Estimate the Execution Time and Consumed Energy of ARM Applications. Carlos Michel Betemps, Mauricio L. Pilla, Julio C. B. Mattos, Lisane B. Brisolara and Bruno Zatt
    16:45 – 17:00: Encoding Energy Control System for Embedded HEVC Applications. Wagner Penny, Ítalo Machado, Marcelo Porto, Luciano Agostini and Bruno Zatt
    17:00 – 17:15: Educational PLC based in Arduino platform. Luciana Rodrigues Cornetet and Cristina Meinhardt

Eventos Sociais

Abertura

Dia 2 de Maio - 17h30
Local: Auditório 1 - CIDEC- SUL, Universidade Federal do Rio Grande
Seguido por coquetel para participantes na EMicro e SIM 2017

Jantar do evento

Dia 4 de Maio - 20h00
Promovido pela IEEE CASS
O jantar está incluso para sócios atuais da IEEE CASS. Os demais participantes são convidados a participar do jantar por adesão.





ORGANIZAÇÃO


Coordenação Geral
Paulo F. Butzen (FURG)
Tiago Balen (UFRGS)
Coordenação do programa SIM
Cláudio Diniz (UCPel)
Eduardo Costa (UCPel)
Coordenação do programa EMICRO
Bruno Zatt (UFPel)
Marcelo Porto (UFPel)
Coordenação Local
Cristina Meinhardt (FURG)
Rafael Schvttiz(FURG)
Coordenação Financeiro
José Rodrigo F. Azambuja (FURG)
Raphael Brum (UFRGS)
Coordenação IEEE CASS
Ricardo Reis (UFRGS)

ORGANIZAÇÃO


Coordenação Geral
Paulo F. Butzen (FURG)
Tiago Balen (UFRGS)
Coordenação do programa SIM
Cláudio Diniz (UCPel)
Eduardo Costa (UCPel)
Coordenação do programa EMICRO
Bruno Zatt (UFPel)
Marcelo Porto (UFPel)
Coordenação Local
Cristina Meinhardt (FURG)
Rafael Schvttiz(FURG)
Coordenação Financeiro
José Rodrigo F. Azambuja (FURG)
Raphael Brum (UFRGS)
Coordenação IEEE CASS
Ricardo Reis (UFRGS)

LOCAL

CIDEC-SUL - UNIVERSIDADE FEDERAL DO RIO GRANDE





Organização








Correalizado por

APOIO